1. Field of the Invention
The present invention relates to a test pattern structure for measuring a misalignment in a semiconductor device fabrication process and a measuring method thereof, and more particularly, to an improved test pattern structure for electrically measuring a misalignment between multi-layer patterns in a semiconductor device fabrication process and a measuring method thereof.
2. Description of the Related Art
Generally, a semiconductor device is fabricated by forming a thin film, etching the thin film to form a first thin film pattern, and forming a second thin film pattern on the first thin film pattern.
Therefore, as the design rule (or size) of the semiconductor devices decrease, the alignment between the lower layer thin film pattern and the upper layer thin film pattern becomes increasingly important. For example, a misalignment between an upper layer thin film pattern and a lower layer thin film pattern may cause a portion where the thin film patterns should be electrically connected to become electrically disconnected. Similarly, an electrical short circuit may be formed in a portion that should be electrically isolated. These misalignments cause the semiconductor device to be defective. Therefore, it is necessary to detect any misalignment and determine if a wafer has a large misalignment that needs to be immediately rectified. Such detection will decrease the fabrication cost.
A conventional misalignment evaluation method will now be explained, beginning with the conventional test pattern structure and fabrication method for evaluating the misalignment.
FIG. 1D illustrates the structure of the test pattern for electrically evaluating the misalignment. Namely, the test pattern structure is formed such that two U-shape portions are closely opposite to each other, thereby forming an elliptical shape. The inverted U-shape portion is positioned in the upper portion, and the U-shape portion is positioned in the lower portion. The left side portion of the inverted U-shape portion is called a leg portion LEG1, and the right side portion of the same is called a leg portion LEG3. In addition, the left side portion of the U-shape is called a leg portion LEG2, and the right side portion of the same is called a leg portion LEG4. The width of the leg portion LEG1 is W1, the width of the leg portion LEG2 is W2, the width of the leg portion LEG3 is W3, and the width of the leg portion LEG4 is W4. The length of the leg portions LEG1 and LEG3 of the inverted U-shape portion is L1, and the length of the leg portions LEG2 and LEG4 of the U-shape portion is L2.
In the conventional test pattern, as shown in FIG. 1A, the conductive layer formed on the semiconductor substrate is etched using a first mask M1, thereby forming the conductive layer pattern having the same shape as the first mask M1 on the semiconductor substrate. In addition, the conductive pattern is partially etched using a second mask M2 as shown in FIG. 1B. After the etching process using the first mask M1, the positions of the semiconductor substrate and the mask are accurately aligned using the second mask M2 during the etching process. With this alignment, the widths W1, W2, W3 and W4 of the leg portions LEG1, LEG2, LEG3 and LEG4 as shown in FIG. 1D are all identical, and the lengths L1 and L2 are identical. FIG. 1C illustrates the resulting structure when the second mask M2 of FIG. 1B is accurately aligned with respect to the first mask M1 of FIG. 1A. The portion indicated by reference numeral 11 in the first mask M1, as shown in FIG. 1A, represents a pattern 11 corresponding to the portion remaining on the semiconductor substrate from the first mask M1 of FIG. 1A, and a pattern 12 corresponding to the open portion 12. In addition, pattern 13 corresponds to a portion remaining on the semiconductor substrate from the second mask M2 of FIG. 1B, and pattern 14 represents an opening portion. In the drawings, the open portion 14 from the second mask M2 is shown by a hatched line.
FIG. 2A illustrates the structure in which the second mask M2 is misaligned with respect to the first mask M1 by a distance "dW" in the leftward direction. FIG. 2B illustrates the structure of the test pattern formed as a result of the misalignment of FIG. 2A. Namely, in the test pattern obtained without any misalignment, the four leg portions of the U-shaped pattern has the identical widths W1, W2, W3 and W4 in FIG. 1D. However, the widths W1 and W4 as shown in FIG. 2B are narrower than the width W by "dW", and the widths W2 and W3 are wider than the width W by "dW". The widths W1 and W4 are identical, and the widths W2 and W3 are identical. In FIG. 2B, points A, B, C and D represent portions from which voltage will be measured to determine the misalignment, as will be discussed later with respect to FIG. 4.
FIGS. 3A through 3H illustrates the fabrication processes for forming the test pattern as shown in FIG. 1D. Namely, FIGS. 3A through 3H illustrate the cross-sectional views taken along the line IIIh--IIIh of FIG. 1D.
As shown in FIG. 3A, an insulation film 102 is formed on a semiconductor substrate 100 (or the wafer). A conductive layer 104 is formed on the insulation film 102. A first photoresist film 106 is formed on the conductive layer 104. Next, as shown in FIG. 3B, a first photoresist film pattern 106a is formed from the photoresist film 106 using the first mask M1 (as shown in FIG. 1A). Thus, the first photoresist film pattern 106a has the same shape as the first mask M1. As shown in FIG. 3C, the conductive layer 104 is etched using the first photoresist film pattern 106a as a mask, thereby forming a conductive layer pattern 104a having the same shape as the first mask M1. Next, the first photoresist film pattern 106a is removed, thereby forming the structure of FIG. 3D. Namely, the conductive layer pattern 104a as shown in FIG. 1A is exposed on the uppermost surface of the semiconductor substrate.
A second photoresist film 108 is formed on the entire structure of FIG. 3D, thereby forming the structure of FIG. 3E. As shown in FIG. 3F, the second photoresist film 108 is patterned using the second mask M2 of FIG. 1B, thereby forming a second photoresist film pattern 108a. At this time, an open portion 14 is formed on the center portion of the conductive layer pattern 104a by patterning the second photoresist film pattern 108a.
Next, the conductive layer pattern 104a exposed through the open portion 14 is etched using the second photoresist film pattern 108a, thereby forming a conductive layer pattern 104b as shown in FIG. 3G. However, in the process of FIG. 3F, if the second mask M2 is accurately aligned on the semiconductor substrate 100 of FIG. 3E, the open portion 14 is formed accurately on a center portion of the conductive layer pattern 104a. Therefore, in the process of FIG. 3G, the widths (W1 and W3) of the left and right sides of the conductive layer pattern 104b with respect to the center of the open portion 14 are same. However, in the process of FIG. 3F, if the second mask M2 is misaligned in the direction of an X-axis, the open portion 14 is formed on a portion moved toward the left side of the conductive layer pattern 104a. Therefore, in the process of FIG. 3G, the width W1 is narrower than the width W3. Then, as shown in FIG. 3H, the second photoresist pattern 108a is removed, thereby forming the structure of the test pattern.
In the test pattern, the principle for measuring the misaligned degree dW is implemented based on the Wheatstone bridge measurement principle. FIG. 4 illustrates a Wheatstone bridge circuit that is equivalent to the test pattern structure of FIGS. 1D or 2B.
The resistances of the resistors R1, R2, R3 and R4 may be computed based on the test pattern of FIG. 2B in the Wheatstone bridge circuit of FIG. 4. The resistance of each resistor R may be computed as R.sub.i =R.sub.s .times.L/W.sub.i (with i=1-4), where R.sub.s represents a sheet resistivity of the conductive layer pattern, L represents the length of a bridge of the U-shape test pattern, and W.sub.i represents the width of the corresponding portion of the bridge of the test pattern. These values may be directly measured based on the test pattern.
As shown in FIG. 2B, there is a misalignment in the direction of the X-axis, and there is not a misalignment in the direction of the Y-axis. Therefore, the lengths of the LEG1, LEG2, LEG3 and LEG4 of the test pattern are all identical and are determined as L. However, W1=W4=W-dW, and W2=W3=W+dW due to the misalignment in the direction of the X-axis, where W represents the width of the bridge of the U-shape pattern, and dW represents a distance of the misalignment in the direction of the X-axis. That is, W is the theoretical value and dW is the shift.
Therefore, in the Wheatstone bridge circuit having a value equal to the circuit shown in FIG. 2B, R1 equals R4 (hereinafter called "R.sub.a "), and R2 equals R3 (hereinafter called "R.sub.b "). The current I.sub.a flowing along the path "a" is identical to the current I.sub.b flowing along the path "b" (in accordance with the characteristic of the Wheatstone bridge) which is I/2, where I represents the current before the bridge.
Therefore, the voltage difference V.sub.o between the point C and the point D is as follows: ##EQU1##
In addition, the voltage V (the voltage difference between the point A and the point B) ##EQU2## passed through the bridge is as follows: ##EQU3##
At this time, since R.sub.a and R.sub.b satisfy the equations: ##EQU4## are obtained, the misalignment may be expressed as follows:
Therefore, if the voltage V.sub.o is zero based on the test pattern, the misalignment dW becomes zero, and it is noted that the thin film pattern between the interlayers is accurately aligned.
However, there is a problem in adapting the misalignment to all fabrication processes for a semiconductor device based on the conventional Wheatstone bridge measuring method in view of the fabrication process of the semiconductor device. Namely, as shown in FIGS. 3A through 3H, it is necessary that a conductive pattern be formed using a first mask pattern and then etched using a second mask pattern. In the conventional art, the identical conductive layers are etched two times before measuring the misalignment. Namely, in the conventional art, the misalignment is not measured using the pattern between the different interlayers.
However, in the conventional processes for fabricating semiconductor devices, such as DRAMs (Dynamic Random Access Memory), the above-described processes are not performed. Namely, there are no processes where an equivalent conductive layer is etched using different masks more than two times. Therefore, during such semiconductor device fabrication, the conventional misalignment measuring method is not suitable since the test pattern is not formed on the wafer. Moreover, since the test wafer is used for measuring the misalignment using the conventional Wheatstone method, the fabrication cost of the semiconductor device is increased.